AnalysisDevelopersNovember 11, 2026

UCSD Hao AI Lab debuts vstack and veriserve for verifiable LLM infra

Read original source →haoailab.com

vstack, a 5-stage formal verification workflow for coding agents, found three classes of RDMA and cache concurrency bugs in SGLang and vLLM, yielding 6 proposed upstream PRs. The veriserve prototype backs its PdLedger design with a 516,973-obligation TLAPS proof at 0.18% mean p50 TPOT overhead on NVIDIA GB200.

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